Alignment processing mechanism and semiconductor processing device using it

ABSTRACT

An alignment processing mechanism  10  according to the present invention includes: a conveying mechanism  11  for conveying a substrate W to be processed, an alignment mechanism  12  for aligning the substrate W conveyed by the conveying mechanism  11  to a predetermined direction, and a buffer mechanism  13  for relaying the substrate W from the conveying mechanism  11  to the alignment mechanism  12 . The buffer mechanism  13  is adapted to temporarily hold the substrate W conveyed by the conveying mechanism  11 , and to pass the temporarily holding substrate W to the alignment mechanism  12  based on a state of the alignment mechanism  12 . According to the present invention, the alignment mechanism  12  can be used with greater efficiency in order to achieve a high speed of an alignment process.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to an alignment processing mechanism and asemiconductor processing unit with the alignment processing mechanism,which can align a substrate to be processed to a predetermined directionbefore processing the substrate.

2. Disclosure of the Prior Art

In semiconductor manufacturing steps, processing units for a singlesubstrate, which is adapted to process the single substrate such as asemiconductor wafer, are widely used. For example, a multi-chamberprocessing unit is known as a processing unit for a single substrate.For example, such a multi-chamber processing unit comprises: a carrierchamber for containing a carrier; an alignment chamber for taking asemiconductor wafer from the carrier contained in the carrier chamberand for conducting an alignment process to the semiconductor wafer; aconveying chamber connected to the alignment chamber via a load-lockchamber; and a plurality of processing chambers arranged around andconnected to the conveying chamber. The plurality of processing chambersare adapted to continuously conduct a predetermined film-forming processor a predetermined etching process. Some multi-chamber processing unitsare adapted to conduct a conveyance of a semiconductor wafer, analignment thereof and a process thereof, consistently under a reducedpressure at a predetermined vacuum level.

Herein, an alignment process is explained. In the alignment chamber, forexample, a semiconductor wafer is taken out from the carrier containedin the carrier chamber via a conveying mechanism under an atmosphericpressure. Then, the semiconductor wafer is conveyed to an alignmentmechanism. The alignment mechanism detects an orientation-flat (ori-fla)of the semiconductor wafer by means of a detector such as an opticalsensor, and conducts an alignment process to the semiconductor wafer.That is, the alignment mechanism turns the semiconductor wafer to apredetermined direction. After conducted the alignment process, thesemiconductor wafer is conveyed from the alignment mechanism to theload-lock chamber via the conveying mechanism. Then, the semiconductorwafer is conveyed from the load-lock chamber to a predeterminedcorresponding processing chamber via the conveying mechanism arranged inthe conveying chamber under a reduced pressure. The semiconductor waferundergoes a predetermined process in the processing chamber. Theprocessed semiconductor wafer is contained in a carrier, which isadapted to contain processed semiconductor wafers, via the conveyingchamber, the load-lock chamber and the alignment chamber.

SUMMARY OF THE INVENTION

However, generally, a speed of the alignment process may be a conditionfor determining a speed of entire sequential processes for thesemiconductor wafer (if a time for which the alignment process isconducted is longer than a time for which the semiconductor wafer isprocessed). Whichever it may or not, in order to raise a throughput, itis an important point to shorten a waiting time (an idle time) of thealignment process. However, as described above, in the case that afterthe alignment process for a previous semiconductor wafer has beencompleted, a next semiconductor wafer is conveyed from the carrierchamber to the alignment mechanism, a time for which the nextsemiconductor wafer is conveyed from the carrier chamber to thealignment mechanism is an idle time of the alignment mechanism. Thus,there is a problem that the throughput is relatively low.

This invention is intended to solve the above problem effectively. Theobject of this invention is to provide an alignment processingmechanism, which can be used with greater efficiency in order to achievesuch a high speed of an alignment process that a throughput may beraised.

In order to achieve the object, an alignment processing mechanismaccording to the invention is characterized by comprising: a conveyingmechanism for conveying a substrate to be processed, an alignmentmechanism for aligning the substrate conveyed by the conveying mechanismto a predetermined direction by causing the substrate to rotate, and abuffer mechanism for relaying the substrate from the conveying mechanismto the alignment mechanism.

According to another feature, the buffer mechanism is adapted totemporarily hold the substrate conveyed by the conveying mechanism andto pass the temporarily holding substrate to the alignment mechanismbased on a situation of the alignment mechanism.

According to another feature, an alignment processing mechanism furthercomprises a second conveying mechanism for conveying the substratealigned by the alignment mechanism.

According to another feature, the buffer mechanism has at least twoholding members for holding the substrate in a vicinity of the alignmentmechanism. In the case, preferably, the holding members are integratedlyable to move vertically with respect to the alignment mechanism, inorder to pass the substrate held thereby to the alignment mechanism. Inaddition, preferably, each of the holding members is adapted to rotatein such a manner that the holding member goes away from a space in whichthe substrate may move. In addition, preferably, each of the holdingmembers has: a supporting surface for coming in contact with andsupporting the reverse surface of the substrate, and a tapered surfaceinclined from the supporting surface and formed correspondingly to anoutside periphery of the substrate.

According to another feature, an alignment mechanism has a stage forbeing placed the substrate, and a driving mechanism for causing thestage to rotate in a horizontal plane.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view of main parts of an embodiment of analignment processing mechanism according to the invention;

FIG. 2 is a sectional view of an entire structure of the embodiment ofthe alignment processing mechanism shown in FIG. 1;

FIG. 3 is a plan view of an example of a processing unit using thealignment processing mechanism shown in FIG. 1; and

FIG. 4 is a plan view of an example of a processing unit using anotherembodiment of an alignment processing mechanism according to theinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Embodiments of the invention will now be described with reference todrawings.

For example, as shown in FIGS. 1 and 2, an alignment processingmechanism 10 of an embodiment of the invention comprises a conveyingmechanism 11 for conveying a semiconductor wafer W, and an alignmentmechanism 12 for aligning the semiconductor wafer W conveyed by theconveying mechanism 11 to a predetermined direction by using anorientation-flat as a standard.

As shown in FIG. 2, the conveying mechanism 11 includes a multi-jointarm 11A which can hold the semiconductor wafer W and which can extendand retract in a horizontal plane, a driving mechanism 11B which cancause the multi-joint arm 11A to rotate in a horizontal plane in regularand reverse directions (θ-direction) and to move in a vertical direction(Z-direction). The conveying mechanism 11 is adapted to adjust a heightof the multi-joint arm 11A to a height for receiving a semiconductorwafer W by means of the driving mechanism 11B, to take out asemiconductor wafer W from a carrier one by one and to convey thesemiconductor wafer W to the alignment mechanism 12. In addition, theconveying mechanism 11 is adapted to convey a semiconductor wafer Wafter conducted an alignment process to a predetermined position. If theconveying mechanism 11 operates under a predetermined vacuum level, itis preferable that the multi-joint arm 11A holds the semiconductor waferW by means of an adsorbing means such as an electrostatic chuck.Alternatively, it is preferable that the multi-joint arm 11A operateswith a semiconductor wafer only placed thereon. If the conveyingmechanism 11 operates under an atmospheric pressure, it is preferablethat the multi-joint arm 11A holds the semiconductor wafer W by means ofa vacuum-adsorbing means. Alternatively, it is preferable that themulti-joint arm 11A operates with a semiconductor wafer placed thereon.

As shown in FIGS. 1 and 2, the alignment mechanism 12 has: a stage 12Afor being placed a semiconductor wafer W, a driving mechanism 12B forcausing the stage 12A to rotate in a regular direction or the reversedirection in a horizontal plane and to vertically move the stage 12A, adetector (not shown) such as an optical sensor for detecting anorientation-flat (including a notch) of the semiconductor wafer W whilethe driving mechanism 12B causes the stage 12A to rotate, and acontroller (not shown) for stopping the driving mechanism 12B in such amanner that the semiconductor wafer W turns to a predetermineddirection. The alignment mechanism 12 is adapted to detect theorientation-flat by means of the detector while causing the stage 12A torotate in the regular direction or the reverse direction, and to alignthe semiconductor wafer W into the predetermined direction by means ofthe controller. If the alignment mechanism 12 operates in apredetermined vacuum state, it is preferable that the stage 12A holdsthe semiconductor wafer W by means of an adsorbing means such as anelectrostatic chuck. Alternatively, if the alignment mechanism 12operates in an atmospheric pressure, it is preferable that the stage 12Aholds the semiconductor wafer W in a vacuum-absorption manner. Inaddition, in FIG. 2, a numerical sign 14 designates a floor plate inwhich the conveying mechanism 11 and the alignment mechanism 12 arearranged.

As shown in FIGS. 1 and 2, the alignment processing mechanism 10 alsocomprises a buffer mechanism 13 for temporarily holding thesemiconductor wafer W. The buffer mechanism 13 is adapted to relay thesemiconductor wafer W from the conveying mechanism 11 to the alignmentmechanism 12. The buffer mechanism 13 has: three supporting pins 13A(holding members) which stand around the stage 12A of the alignmentmechanism 12 at substantially regular intervals in a peripheraldirection thereof and whose upper portions have holding members 13G thatcan support a reverse surface of the semiconductor wafer W respectively,a ring-shaped connecting member 13B for connecting and unifying lowerends of the supporting pins 13A with each other in such a manner thateach of the supporting pins 13A can rotate relatively to the connectingmember 13B, and an elevating mechanism 13C (for example, an aircylinder) connected to the connecting member 13B. The air cylinder 13Cis fixed below the floor plate 14 and adapted to cause the holding pins13A to vertically move integratedly between upper and lower portions forpassing or receiving the semiconductor wafer W. Then, the threesupporting pins 13A are adapted to hold the semiconductor wafer W insuch a manner that a center of the semiconductor wafer W is located onan extending line of an axis of the stage 12A of the alignment mechanism12. Thus, when the three supporting pins 13A are caused to move downwardby means of the air cylinder 13C, the semiconductor wafer W is passedonto the stage 12A in such a manner that the center of the semiconductorwafer W is located on a center of the stage 12A.

The holding members 13G are fixed to the supporting pins 13A at upperends of the supporting pins 13A, respectively. In an upper surface ofeach of the holding members 13G, a supporting surface 13H for supportingthe semiconductor wafer W and a tapered surface 13I inclined from thesupporting surface 13H to an outside periphery of the semiconductorwafer W are formed. Thus, the tapered surface 13I functions as a guidesurface for guiding the semiconductor wafer onto the supporting surface13H. Each of the holding members 13G may be formed integrally with acorresponding supporting pin 13A.

A line defined by a boundary between the tapered surface 13I and thesupporting surface 13H may be a straight line perpendicular to adiameter of the semiconductor wafer W or an arc correspondingly to theoutside periphery of the semiconductor wafer W. That is, it is enoughfor the line to substantially correspond the outside periphery of thesemiconductor wafer W.

However, each of the supporting pins 13A is connected to the connectingmember 13B in a manner rotatable in the regular and the reversedirections. Then, a pulley 13D is attached to each of the supportingpins 13A, a motor 13E rotatable in a regular and the reverse directionsis attached to the connecting member 13B, and an endless belt 13F isrolled around the pulley 13D and an output pulley of the motor 13E.Thus, as shown by an arrow in FIG. 2, each of the supporting pins 13A isadapted to rotate in the regular or the reverse direction via theendless belt 13F when the motor 13E rotates in the regular or thereverse direction.

Each of the holding members 13G turns to an inside direction or anoutside direction relative to an area surrounded by the supporting pins13A depending on it that each of the supporting pins 13A rotates in theregular or the reverse direction. When each of the holding members 13Gturns to the outside direction, the holding members 13G are evacuatedoutside from a relative moving space of the semiconductor wafer W. Thatis, the holding members are arranged in such a manner that thesemiconductor wafer W can relatively vertically move among thesupporting pins 13A.

The supporting pins 13A are arranged around the stage in such a mannerthat an inscribed circle of the supporting pins 13A can surround thesubstrate. It is preferable that at least one of intervals between anytwo of the supporting pins 13A is an interval through which thesubstrate held by the conveying means can move. According to thestructure, the conveying means can take out an aligned substrate from onthe stage with the holding members holding the aligned substrate.

In the embodiment, the number of the supporting pins is three, but theinvention is not limited by the manner. The invention can adopt onesupporting pin that can support a circular holding member. In addition,the invention can adopt two or four or more supporting pins. However, ifthe holding member is supported by the one supporting pin, a movementfor evacuating the holding member from the moving space of the substratetends to be large. Thus, there is a drawback that a time for themovement tends to be long. In the view of this, it is preferable that aplurality of supporting pins support a plurality of holding members. Iffour supporting pins are arranged, it is preferable that the foursupporting pins are arranged at corners of a rectangle (including asquare) surrounding the stage, respectively, and that two intervalsbetween the supporting pins 13A corresponding to two longer sides of therectangle are intervals through which the substrate held by theconveying means can move. In the case, the substrate can be transferredonto or from on the stage on both opposite sides of the stage.

Next, a multi-chamber processing unit (hereafter, it is abbreviated as“processing unit”) using the above alignment high-speed processingmechanism 10 is described with reference to FIG. 3. As shown in FIG. 3,the processing unit 20 comprises: right and left carrier chambers 21 forcontaining semiconductor wafers W every carrier; an alignment chamber 22located between them; a conveying chamber 23 having seven side surfaces,adjacent three of which are connected to the carrier chambers 21 and thealignment chamber 22, respectively; and four processing chambers 24connected to the rest four side surfaces of the conveying chamber 23,respectively. In the processing unit 20, conveyance and alignment of thesemiconductor wafer W are adapted to be conducted in a predeterminedvacuum state.

The alignment mechanism 12 and the buffer mechanism 13 of the alignmentprocessing mechanism 10 are arranged in the alignment chamber 22,respectively. The conveying mechanism arranged in the conveying chamberconveys the wafer to the alignment processing mechanism. Thus, beforethe semiconductor wafer W undergoes a process in the processing chambers24, the alignment process for the semiconductor wafer W can be conductedat a high speed. One of the processing chambers 24 may be for example aplasma-processing chamber, wherein a predetermined circuit film or apredetermined insulating film may be formed on a surface of thesemiconductor wafer W and/or unnecessary portion of the formed film maybe removed.

Next, an operation of the processing unit 20 is described. At first, thecarrier chambers 21, the alignment chamber 22, the conveying chamber 23and the processing chambers 24 are produced a vacuum. Each of thechambers is maintained at a predetermined reduced pressure,respectively. Then, the semiconductor wafer W is conveyed and alignedunder the predetermined reduced pressure. That is, the conveyingmechanism 11 operates so that the multi-joint arm 11A extends and/orretracts via the driving mechanism 11B to take out a semiconductor waferW from a carrier C in a carrier chamber 21 into the conveying chamber23. Then, the multi-joint arm 11A is caused to rotate so that thesemiconductor wafer W turns to the buffer mechanism 13 as shown by reallines in FIG. 1. At that time, the multi-joint arm 11A and each of thesupporting pins 13A are caused to vertically move relative to each otherso that the height of the multi-joint arm 11A and the heights of thesupporting pins 13A are adjusted for enabling the semiconductor wafer tobe passed between the multi-joint arm 11A and the supporting pins 13A.

Then, the multi-joint arm 11A extends to convey the semiconductor waferW just above the holding members 13G of the three supporting pins 13A.After that, the multi-joint arm 11A is caused to move downward a littlevia the driving mechanism 11B so that the semiconductor wafer W ispassed to the buffer mechanism 13 as shown by dashed lines in FIG. 2. Atthat time, all the holding members 13G of the supporting pins 13A turnto the inside direction. Thus, the three supporting surfaces 13H supporta peripheral area of the reverse surface of the semiconductor wafer W.Then, the multi-joint arm 11A moves back from the buffer mechanism 13.Even if a position of the semiconductor wafer W and positions of thesupporting pins 13A are not coincident a little when the semiconductorwafer W is passed to the buffer mechanism 13, the semiconductor wafer Wis guided onto the respective supporting surfaces 13H by the respectivetapered surfaces 13I of the holding members 13G. Thus, the threesupporting pins 13A can surely support the semiconductor wafer W bymeans of the supporting surfaces 13H.

When the buffer mechanism 13 receives the semiconductor wafer W, the aircylinder 13C operates so that each of the supporting pins 13A is causedto move downward to a position for passing the semiconductor wafer Wonto the stage 12A. Then, the semiconductor wafer W is placed on thestage 12A. Then, the stage 12A is caused to move upward a little withholding the semiconductor wafer W, and to rotate. While the stage 12A isrotated, the detector detects the orientation-flat of the semiconductorwafer W and the controller controls rotation of the stage 12A to alignthe semiconductor wafer W.

During the alignment process, the buffer mechanism 13 and the conveyingmechanism 11 operates. That is, the motor 13E of the buffer mechanism 13operates to cause the three supporting pins 13A to rotate, for exampleby 180 degrees, via the endless belt 13F. Thus, the supporting surfaces13H of the holding members 13G turn to the outside direction of thesemiconductor wafer W, respectively. After the holding members 13G areevacuated from the semiconductor wafer W, each of the supporting pins13A is caused to move upward to a position for receiving thesemiconductor wafer W from the conveying mechanism 11, by means of theair cylinder 13C. Then, a next semiconductor wafer W conveyed from thecarrier chamber 21 by the conveying mechanism 11 is passed to the buffermechanism 13 via the multi-joint arm 11A, in the same way as describedabove. The next semiconductor wafer W is temporarily held by the buffermechanism 13, in the same way as described above.

After the alignment process for the semiconductor wafer W is completedin the alignment chamber 22, the multi-joint arm 11A of the conveyingmechanism 11 is caused to move downward to a position for receiving thesemiconductor wafer W from on the stage 12A, by means of the drivingmechanism 11B. The multi-joint arm 11A extends to the stage 12A as shownby real lines in FIG. 2, to receive the semiconductor wafer W that hasbeen aligned. Then, the multi-joint arm 11A moves back together with thesemiconductor wafer W from the alignment chamber 22, and conveys thesemiconductor wafer W into a predetermined processing chamber 24. Afterthe multi-joint arm 11A has moved back from the processing chamber 24, aprocess for the semiconductor wafer W starts in the processing chamber24. Just after the multi-joint arm 11A has received the semiconductorwafer W from on the stage 12A, the buffer mechanism 13 operates to passthe next semiconductor wafer W, which has been temporarily held thereby,onto the stage 12A in the same way as described above. Then, thealignment mechanism 12 conducts an alignment process for the nextsemiconductor wafer W.

During the alignment process, the conveying mechanism 11 may convey thesemiconductor wafer W from the carrier chamber 21 to the buffermechanism 13, or may convey the processed semiconductor wafer W from theprocessing chamber 24 to a carrier C for containing processedsemiconductor wafers W contained in the other carrier chamber 21. Afterthe alignment process, as described above, just after the semiconductorwafer W has been taken out, the next semiconductor wafer is passed fromthe buffer mechanism 13 to the alignment mechanism 12.

As described above, according to the embodiment, since the buffermechanism 13 is provided for temporarily holding the semiconductor waferW just before undergoing the alignment process, the next semiconductorwafer W can be passed from the conveying mechanism 11 to the buffermechanism 13 while the alignment process for the former semiconductorwafer W is conducted in the alignment mechanism 12. Thus, just after thealignment process for the former semiconductor wafer W has beencompleted, the alignment process for the next semiconductor wafer W canbe started. That is, a waiting time of the alignment mechanism 12 can beremoved or shortened so that the alignment mechanism 12 can becontinuously used more efficiently. Thus, the alignment process for thesemiconductor wafer W can be conducted at a high speed. Therefore,throughput for processing the semiconductor wafer W can be raised.

FIG. 4 is a plan view of a processing unit 30 applying anotherembodiment of an alignment processing mechanism 10 according to theinvention. As shown in FIG. 4, the processing unit 30 comprises: rightand left carrier chambers 31 for containing semiconductor wafers W everycarrier; an alignment chamber 32 located between them; a conveyingchamber 35 connected to the alignment chamber 32 via right and leftload-lock chambers 33, 34; and processing chambers 36 connected to therest side surfaces of the conveying chamber 35, respectively. In theprocessing unit 30, an alignment process for the semiconductor wafer Wis adapted to be conducted under an atmospheric pressure.

The alignment processing mechanism 10A of the embodiment comprises asecond conveying mechanism 35A arranged in the conveying chamber 35besides a conveying mechanism 11, an alignment mechanism 12 and a buffermechanism 13. A feature of conveying a semiconductor wafer W beforealigned to the buffer mechanism 13 via the conveying mechanism 11 is thesame as the previous embodiment. However, a feature of conveying asemiconductor wafer W after aligned via the second conveying mechanism35A is different from the previous embodiment. That is, although theconveying mechanism 11 of the previous embodiment has an elevatingmechanism that can cause the multi-joint arm 11A to vertically move, theconveying mechanism 11, 35A of the embodiment don't have an elevatingmechanism that can cause the multi-joint arm to vertically move. In theembodiment, respective multi-joint arms pass and/or receive asemiconductor wafer W at respective predetermined constant heights. Inaddition, in the alignment processing mechanism 10A, the semiconductorwafer W is adapted to be aligned under the atmospheric pressure asdescribed above, and the semiconductor wafer W after aligned is adaptedto be conveyed in a predetermined vacuum state.

Supporting pins 13A are arranged around a stage in such a manner that aninscribed circle of the supporting pins 13A can surround the substrate.It is preferable that at least one of intervals between any two of thesupporting pins 13A is an interval through which the substrate held bythe conveying means can move. According to the structure, the conveyingmeans can take out an aligned substrate from on the stage with holdingmembers holding the aligned substrate.

In the embodiment, the number of the supporting pins is three, but theinvention is not limited by the manner. The invention can adopt onesupporting pin that can support a circular holding member. In addition,the invention can adopt two or four or more supporting pins. However, ifthe holding member is supported by the one supporting pin, a movementfor evacuating the holding member from a moving space of the substratetends to be large. Thus, there is a drawback that a time for themovement tends to be long. In the view of this, it is preferable that aplurality of supporting pins support a plurality of supporting members.If four supporting pins are arranged, it is preferable that the foursupporting pins are arranged at corners of a rectangle (including asquare) surrounding the stage, respectively, and that two intervalsbetween the supporting pins 13A corresponding to two longer sides of therectangle are intervals through which the substrate held by theconveying means can move. In the case, the substrate can be moved ontoor from on the stage on both opposite sides of the stage.

The multi-joint arm 11 takes out a first semiconductor wafer W from acarrier C containing a plurality of semiconductor wafers and puts thefirst semiconductor wafer W on the stage 12A of the alignment mechanism.While the first semiconductor wafer W is aligned, the multi-joint arm 11takes out a second semiconductor wafer W from the carrier C and passesthe second semiconductor wafer W to the holding members of thesupporting pins 13A. After an alignment process for the firstsemiconductor wafer W is completed, the multi-joint arm 11 takes out thefirst semiconductor wafer W from on the stage 12A, and conveys the firstsemiconductor wafer W into the load-lock chamber 33. The nextsemiconductor wafer W temporarily held by the supporting pins 13A isimmediately conveyed onto the stage 12A and undergoes an alignmentprocess. While the alignment process, the multi-joint arm takes out athird semiconductor wafer W from the carrier C, and passes the thirdsemiconductor wafer W to the supporting pins 13A. The load-lock chamber33 is closed after the first semiconductor wafer W is conveyedthereinto. Then, an inside of the load-lock chamber 33 is vacuumed to apredetermined vacuum level. Then, a gate of the load-lock chamber 33 ona side of a multi-joint arm 35A is opened, and the first semiconductorwafer W is taken out by the multi-joint arm 35A. The semiconductor waferW is conveyed into a predetermined processing chamber 36 by themulti-joint arm 35A to undergo a predetermined process. Thesemiconductor wafer W after undergoing the process is taken out from theprocessing chamber by the multi-joint arm 35A, and is conveyed via theload-lock chamber 34 to the carrier C by the multi-joint arm 11.

The embodiment also has the same functions and effects as the previousalignment processing mechanism 10.

As another embodiment of a semiconductor processing unit, besides thealignment mechanism described above, a system may further comprise acontaining means for containing substrates and a processing chamber forprocessing the substrates, wherein the containing means, the alignmentmeans and the processing chamber may be arranged on substantially thesame straight line. In a typical example, a wafer-carrier as acontaining means, an alignment mechanism and a processing chamber arearranged in that order. If necessary, a load-lock means are arrangedbetween the alignment mechanism and the processing chamber.

A conveying means is provided in a vicinity of the alignment mechanism.If the unit has the load-lock means, another conveying means is providedbetween the load-lock means and the processing chamber.

In addition, in each of the embodiments described above, when thesemiconductor wafer W is passed from the buffer mechanism 13 to thealignment mechanism 12, the supporting pins 13A of the buffer mechanism13 rotate so that the supporting members 13G are evacuated from thesemiconductor wafer W. However, the supporting pins 13A may be arrangedin such a manner that each of the supporting pins 13A can move in aradial direction of the semiconductor wafer W. Alternatively, thesupporting pins 13A may be arranged in such a manner that each upper endof the supporting pins 13A can tilt outward in order to evacuate thesupporting member from the moving space of the semiconductor wafer. Inaddition, it is enough that the alignment mechanism 12 and the buffermechanism 13 can vertically move with respect to each other, that is, itis not necessary for the alignment mechanism 12 to have an elevatingmechanism.

In each of the embodiments described above, the buffer mechanism holdsthe substrate right above the stage. In the case, the buffer mechanismhas to move only in a vertical direction in order to pass the substrateonto the stage. Thus, the embodiments have an advantage of a lesshorizontal positional error. However, the invention is not limited bythe manner. It is enough that a position for the buffer mechanism totemporarily hold the substrate is near the stage. For example, theposition may be located diagonally above the stage. In the case, it isnecessary to provide a means for causing the buffer mechanism to move ina diagonal downward direction when the substrate is passed onto thestage.

As a typical semiconductor processing unit using the invention, thereare a CVD unit and a plasma etching unit. In addition, the invention canbe used in a wafer-prober, a coater-developper, a pattern-exposure unit,or any general unit necessary to conduct any alignment process to asubstrate.

In each of the embodiments described above, the multi-joint arm is usedas the conveying means. However, a belt-conveying mechanism may be used.

In each of the embodiments described above, the processing unit is avacuum processing unit for the semiconductor wafer. However, theinvention may be used in a processing unit for a square substrate suchas a substrate for a liquid-crystal display. In addition, besides thevacuum processing unit, the invention may be widely used in any generalsemiconductor processing unit including a semiconductor manufacturingunit and a semiconductor testing unit, which is necessary to conduct analignment process to a substrate.

What is claimed is:
 1. An alignment processing mechanism comprising: aconveying mechanism for conveying a substrate to be processed, analignment mechanism for detecting an orientation-flat of the substrateconveyed by the conveying mechanism and for aligning theorientation-flat to a predetermined direction by causing the substrateto rotate, and a buffer mechanism for relaying the substrate from theconveying mechanism to the alignment mechanism, wherein the buffermechanism temporarily holds the substrate conveyed by the conveyingmechanism, and passes the substrate to the alignment mechanism bychanging a relative position of the substrate to the alignment mechanismbased on a state of the alignment mechanism, in such a manner that acenter of the substrate is located on a rotational axis of the alignmentmechanism.
 2. An alignment processing mechanism according to claim 1,further comprising: a second conveying mechanism for conveying thesubstrate aligned by the alignment mechanism.
 3. An alignment processingmechanism according to claim 1, wherein: the buffer mechanism has atleast two holding members for holding the substrate in a vicinity of thealignment mechanism.
 4. An alignment processing mechanism according toclaim 3, wherein: the holding members are integratedly able to movevertically with respect to the alignment mechanism, in order to pass thesubstrate held thereby to the alignment mechanism.
 5. An alignmentprocessing mechanism according to claim 3, wherein: each of the holdingmembers has a supporting member for supporting a reverse surface of thesubstrate.
 6. An alignment processing mechanism according to claim 5,wherein: the supporting member of each of the holding member is adaptedto rotate in such a manner that the supporting member goes away from thereverse surface of the substrate.
 7. An alignment processing mechanismaccording to claim 6, wherein: each of the holding members has: asupporting surface for coming in contact with and supporting the reversesurface of the substrate, and a tapered surface inclined from thesupporting surface and formed correspondingly to an outside periphery ofthe substrate.
 8. An alignment processing mechanism according to claim7, wherein: an alignment mechanism has a stage for being placed thesubstrate, and a driving mechanism for causing the stage to rotate in ahorizontal plane.
 9. A semiconductor processing unit comprising: analignment means for placing a substrate to be processed onto a stage,for detecting an orientation-flat of the substrate, and for aligning theorientation-flat to a predetermined direction by causing the stage torotate, a buffer means for temporarily holding another substrate in avicinity of the stage while the alignment process is conducted, a meansfor moving the stage and the buffer means relatively to each other andplacing the substrate held by the buffer means onto the stage in such amanner that a center of the substrate is located on a rotational axis ofthe stage, and at least a conveying moans for passing or receiving thesubstrate to or from the alignment means and/or the buffer means.
 10. Asemiconductor processing unit according to claim 9, wherein: the buffermeans has: a plurality of holding members arranged around the stage andcapable of holding the substrate, and a means for switching a positionof the plurality of holding members between a first position wherein theplurality of holding members hold the substrate and a second positionwherein the plurality of holding members are away from a space in whichthe substrate may move.
 11. A semiconductor processing unit according toclaim 10, wherein: each of the plurality of holding members is providedat an upper portion of each of a plurality of supporting membersvertically standing around the stage and at substantially regularintervals with respect to a peripheral direction, and at least one ofintervals between any two of the plurality of supporting members under asituation that the plurality of holding members are located higher thanthe stage is an interval through which the substrate held by theconveying means can move.
 12. A semiconductor processing unit accordingto claim 10, wherein: each of the plurality of holding members has aholding surface for supporting a peripheral portion of a reverse surfaceof the substrate when the plurality of holding members are located atthe first position, and a tapered portion formed by a slope extendingoutward and upward from the holding surface, and a border between theholding surface and the tapered portion forms a line substantiallycorresponding to an outside periphery of the substrate while thesubstrate is held.
 13. A semiconductor processing unit according toclaim 9, further comprising: a first conveying means for passing thesubstrate to the buffer means, and a second conveying means forreceiving the substrate from the stage.
 14. A semiconductor processingunit according to claim 9, further comprising: a containing means forcontaining a plurality of substrates, and a processing chamber forconducting a process to a substrate, wherein the containing means, thealignment means and the processing chamber are arranged on substantiallya straight line.
 15. A semiconductor processing unit according to claim9, further comprising: a plurality of containing means, each of which isadapted to contain a plurality of substrates, and a plurality ofprocessing chambers, each of which is adapted to conduct a process to asubstrate, wherein the plurality of containing means, the alignmentmeans and the plurality of processing chambers are arranged around theconveying means.
 16. A semiconductor processing unit according to 9,further comprising: an alignment chamber having the alignment means, thebuffer means and a first conveying means, a containing means arrangedadjacently to the alignment chamber, for containing the substrate, aload-lock means arranged adjacently to the alignment chamber, aconveying chamber arranged adjacently to the load-lock means, having asecond conveying means, and a vacuum processing chamber arrangedadjacently to the conveying chamber, for conducting a vacuum process tothe substrate, wherein the first conveying means removes the substratefrom the containing means, passes the substrate to the buffer means,receives the substrate from the stage of the alignment means and conveysthe substrate to the load-lock means, and the second conveying meansreceives the substrate from the load-lock means and conveys thesubstrate to the vacuum process chamber.
 17. An alignment processingmechanism comprising: a conveying mechanism for conveying a substrate tobe processed, an alignment mechanism for aligning the substrate conveyedby the conveying mechanism to a predetermined direction by causing thesubstrate to rotate, and a buffer mechanism for relaying the substratefrom the conveying mechanism to the alignment mechanism, wherein thebuffer mechanism is adapted to temporarily hold the substrate conveyedby the conveying mechanism, and to pass the temporarily holdingsubstrate to the alignment mechanism by changing a relative position ofthe substrate to the alignment mechanism based on a state of thealignment mechanism, in such a manner that a center of the substrate islocated on a rotational axis of the alignment mechanism, wherein thebuffer mechanism surrounds a space through which the alignment mechanismis moved.